The invention relates generally to semiconductor devices and more particularly to thermally enhanced semiconductor devices.
In many integrated circuits, designers go to great lengths to match the characteristics of devices, particularly for analog applications. One way in which designers often attempt to “match” two transistors is by matching their geometries (i.e., layouts). By doing this, the transistors experience similar electrical stresses with respect to surrounding devices. Therefore, the two transistors may have similar gains (β), currents delivered (IDs), voltage thresholds (VT), etc.
Even with matched geometries, however, it is still difficult to achieve extremely precise transistor matching over time due to dynamic temperature variations between two matched devices. For example, at any given time one transistor of a matched pair of transistors may draw a much larger current than the other transistor. This large current may cause the transistor or its surrounding structures to heat up more than the other transistor, thereby creating a thermally induced offset (or “thermal drift”) between the two devices. This thermally induced offset may vary as a function of time and is particularly problematic between devices where precise matching is desired.